pyVHDLModel 0.10.5

An abstract VHDL language model.

pyVHDLModel

An abstract VHDL language model written in Python.

Main Goals

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.

Use Cases

pyVHDLModel Generators

• High-level API for GHDL's libghdl offered via pyghdl.
• Code Document-Object-Model (Code-DOM) in pyVHDLParser.

pyVHDLModel Consumers

• Create graphical views of VHDL files or designs.
  Possible candidates: Symbolator
• Created a (re)formatted output of VHDL.

Examples

List all Entities with Generics and Ports

The following tiny example is based on GHDL's pyGHDL.dom package implementing pyVHDLModel.

from pathlib import Path
from pyGHDL.dom.NonStandard import Design, Document

sourceFile = Path("example.vhdl")

design = Design()
library = Design.GetLibrary("lib")
document = Document(sourceFile)
design.AddDocument(document, library)

for entity in document.Entities:
  print("{}".format(entity.Name))
  print("  generics:")
  for generic in entity.Generics:
    print("  - {} : {!s} {}".format(
      generic.Name, generic.Mode, generic.SubTypeIndication)
    )
  print("  ports:")
  for port in entity.Ports:
    print("  - {} : {!s} {}".format(
      port.Name, port.Mode, port.SubTypeIndication)
    )

Contributors

• Patrick Lehmann (Maintainer)
• Unai Martinez-Corral
• and more...

License

This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).

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SPDX-License-Identifier: Apache-2.0