10 projects
librelane
An infrastructure for implementing chip design flows
ciel
An PDK builder/version manager for PDKs in the open_pdks format
nl2bench
Converts from combinational netlists to the BENCH format for DFT
lln-libparse
Python wrapper around Yosys' libparse module
fault-dft
Open source DFT toolchain
openlane
An infrastructure for implementing chip design flows
volare
An PDK builder/version manager for PDKs in the open_pdks format
ioplace-parser
Antlr4-based parser for the OpenLane I/O Placement script
libparse
Python wrapper around Yosys' libparse module
spef-extractor
A parasitics estimator based on layout and technology files.
