Parse and elaborate front-end for SystemRDL 2.0

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  • License: MIT License (MIT)
  • Author: Alex Mykyta
  • Tags SystemRDL , CSR , compiler , tool , registers , generator , register abstraction layer , FPGA , ASIC
  • Requires: Python >=3.7
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SystemRDL Compiler

The systemrdl-compiler project implements a generic compiler front-end for Accellera's SystemRDL 2.0 register description language. The goal of this project is to provide a free and open compiler that lowers the barrier to entry to using an industry standard register description language.

By providing an elaborated register model that is easy to traverse and query, it should be far easier to write custom register space view generators.

overview

Documentation

See the SystemRDL Compiler Documentation for more details

Related Projects

If you are looking for a complete SystemRDL command line tool, see the PeakRDL project.

License

The SystemRDL Compiler is published and distributed under the MIT License.

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  • License: MIT License (MIT)
  • Author: Alex Mykyta
  • Tags SystemRDL , CSR , compiler , tool , registers , generator , register abstraction layer , FPGA , ASIC
  • Requires: Python >=3.7
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This version

1.32.2

1.32.1

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